library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;


entity comparator is
generic (N : integer := 32);
port(	data_0 : in std_logic_vector (N-1 downto 0);
		data_1 : in std_logic_vector (N-1 downto 0);
		CMP_LT : out std_logic;
		CMP_EQ : out std_logic;
		CMP_GT : out std_logic
);
end comparator;

architecture Behavioral of comparator is
component cmp is
generic (N : integer := 32);
port( 	CMP_DFF : in std_logic_vector (N-1 downto 0);
		CMP_LT  : out std_logic;
		CMP_EQ  : out std_logic;
		CMP_GT  : out std_logic
);
end component;

component RCA is
generic(N : integer := 8);
port(	A_rca	: in   std_logic_vector (N-1 downto 0);
		B_rca	: in   std_logic_vector (N-1 downto 0);
		S_rca	: out std_logic_vector (N-1 downto 0);
		C_i		: in   std_logic;
		C_o		: out std_logic
);
end component;

signal result: std_logic_vector(N-1 downto 0);
signal data_tmp: std_logic_vector(N-1 downto 0);
begin

data_tmp <= not data_1;
--B_rca = not(data_1)+1 = -data_1
SUB: RCA generic map(N) port
map (	A_rca	=> data_0,
		B_rca	=> data_tmp, 
		S_rca	=> result,
		C_i		=> '1',
		C_o		=> open);

COMP: cmp generic map(N) port
map (result,CMP_LT,CMP_EQ,CMP_GT);

end Behavioral;

